An ongoing research focusing on developing an auxiliary tool for designing embedded system. This research proposes a tag-based approach to eliminate the gap between higher-level block diagrams and schematic diagrams. At the same time, it verifies the user's design and provides editing suggestions to improve the efficiency of the design flow.

My main role in this project is to create a multi-resolution hardware-software co-simulation model utilizing Discrete Event Simulation (DES) to verify designs created by Sysmaker.