RISC-V CPU on FPGA

A self-designed single-cycle RISC-V CPU with UART as I/O on FPGA using Verilog, which execute prebuilt executables and output through the UART device. This project involved a comprehensive design process, including hardware design and implementation, simulation, and verification.

This project is a team effort, and my main role in this project is responsible for the design and implementation of the CPU component.

Relevant Skills

Verilog UART GNU-toolchain RISC-V Logic Design Computer Archetechture